`timescale 1ps / 1ps

module div
#(
    parameter integer D_W = 32
)
(
    input  logic           clk,
    input  logic           rst,
    input  logic           enable,
    input  logic           in_valid,
    input  logic [D_W-1:0] divisor,
    input  logic [D_W-1:0] dividend,
    output logic [D_W-1:0] quotient,
    output logic           out_valid
);

// Your solution here.
enum {INIT, COMP} state;

// Internal registers
// use LOPD (leading one position detect) for floor log2
// msb also here because it is the same size as divisor_log2 and remainder_log2
logic [$clog2(D_W)-1:0] divisor_log2, remainder_log2, msb;
// intermediate registers
logic [D_W-1:0] remainder, A, B;
logic [D_W-1:0] divisor_r, remainder_r, quotient_r;

lopd #(.D_W(D_W)) floor_log2_divisor(.in_data(divisor_r), .out_data(divisor_log2));
lopd #(.D_W(D_W)) floor_log2_remainder(.in_data(remainder), .out_data(remainder_log2));

// combinational logic (the stuff in the while loop)
always_comb begin
    remainder_r = remainder;
    quotient_r = quotient;

    msb = remainder_log2 - divisor_log2;
    A = (divisor_r << msb);
    B = A >> 1;

    if (remainder < A) begin
        remainder_r = remainder_r - B;
        quotient_r = quotient_r + (1 << (msb-1));
    end else begin
        remainder_r = remainder_r - A;
        quotient_r = quotient_r + (1 << msb);
    end

    // if (remainder >= divisor_r) begin
    //     if(remainder < A) begin
    //         remainder_r = remainder_r - B;
    //         quotient_r = quotient_r + (1 << (msb-1));
    //     end else begin
    //         remainder_r = remainder_r - A;
    //         quotient_r = quotient_r + (1 << msb);
    //     end
    // end
    // else begin
    
    // end
end

// sequential logic (manages all the states here)
always_ff @(posedge clk) begin

    if (rst) begin
        // reset all registers in design to 0
        divisor_r <= 0;
        quotient <= 0; 
        remainder <= 0;
        out_valid <= 0;
        state <= INIT;
    end
    else begin
        if (enable) begin
            case (state)
            INIT: begin
                out_valid <= 0;
                if (in_valid) begin
                    remainder <= dividend;
                    divisor_r <= divisor;
                    quotient <= 0;
                    state <= COMP;
                end
                else begin
                        state <= INIT;
                end
            end
            COMP: begin
                remainder <= remainder_r;
                quotient <= quotient_r;
                if (remainder_r >= divisor_r) begin
                    out_valid <= 0;
                    state     <= COMP;
                    // stay in COMP to do another "iteration"
                end
                else begin
                    out_valid <= 1;
                    state     <= INIT;
                end
            end
            endcase
        end
    end
end

endmodule